Building a New Data Storage Memory – Eurasia Review


Scientists from the University of Tokyo’s Institute of Industrial Sciences fabricated vertically formed three-dimensional field-effect transistors to produce high-density data storage devices by a ferroelectric gate insulator and a semiconductor channel of oxide deposited on an atomic layer. Additionally, by using an antiferroelectric instead of a ferroelectric, they found that only a tiny net charge was needed to erase the data, leading to more efficient write operations. This work may enable a new, even smaller and greener data storage memory.

While consumer flash drives already offer huge improvements in size, capacity, and accessibility over previous computer media formats in terms of data storage, new machine learning and big data applications continue to drive the demand for innovation. In addition, cloud-enabled mobile devices and future Internet of Things nodes will require small, energy-efficient memory. However, current flash memory technologies require relatively large currents to read or write data.

Today, a team of researchers from the University of Tokyo has developed a proof-of-concept 3D stacked memory cell based on ferroelectric and antiferroelectric field-effect transistors (FETs) with a deposited oxide semiconductor channel on an atomic layer. These FETs can store ones and zeros non-volatile, meaning they do not require power at all times. The device’s vertical structure increases information density and reduces operating power requirements. Hafnium oxide and indium oxide layers were deposited in a vertical trench structure. Ferroelectric materials have electric dipoles that are most stable when aligned in the same direction. The ferroelectric hafnium oxide spontaneously allows the vertical alignment of the dipoles. Information is stored by the degree of polarization in the ferroelectric layer, which can be read by the system due to changes in electrical resistance. On the other hand, antiferroelectrics like to alternate up and down dipoles in the erased state, which enables efficient erasing operations in the semiconductor oxide channel.

“We showed that our device was stable for at least 1,000 cycles,” says first author Zhuo Li.

The team experimented with different thicknesses for the indium oxide layer. They found that optimizing this setting can lead to significant performance increases. The researchers also used first-principles-based computer simulations to plot the most stable surface states.

“Our approach has the potential to significantly improve the field of nonvolatile memory,” says lead author Masaharu Kobayashi. This type of research using both experimental prototypes coupled with computer simulations can help enable the consumer electronics of the future.

The work is published in 2022 IEEE Silicon Nanoelectronics Workshop as “A vertical channel ferroelectric/anti-ferroelectric FET with ALD InOx and field-induced polar axis alignment for high-density 3D memory”.

This work was supported by JST’s Intellectual Property Utilization Support Program, Super-Highway, Japan.

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